UPD70F3451GC-UBT-A Datasheet, PDF (366/1191 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
(2) Operation timing in one-shot pulse output mode
(a) Note on rewriting TABnCCRa register
To change the set value of the TABnCCRa register to a smaller value, stop counting once, and then
change the set value. When the overflow may occur, stop counting once, and then change the set value.
FFFFH
16-bit counter
0000H
TABnCE bit
External trigger input
(TRGBn pin input)
TABnCCR0 register
INTTBnCC0 signal
TOBn0 pin output
TABnCCRb register
INTTBnCCb signal
TOBnb pin output
D00
Db0
D00
D01
Db0
Db1
D01
Db1
D00
D01
Db0
Db1
Delay
(Db0)
Active level width
(D0 − Db0 + 1)
Delay
(10000H + Db1)
Delay
(Db1)
Active level width
(D01 − Db1 + 1)
Active level width
(D01 − Db1 + 1)
When the TABnCCR0 register is rewritten from D00 to D01 and the TABnCCRb register from Db0 to Db1
where D00 > D01 and Db0 > Db1, if the TABnCCRb register is rewritten when the count value of the 16-bit
counter is greater than Db1 and less than Db0 and if the TABnCCR0 register is rewritten when the count
value is greater than D01 and less than D00, each set value is reflected as soon as the register has been
rewritten and compared with the count value. The counter counts up to FFFFH and then counts up again
from 0000H. When the count value matches Db1, the counter generates the INTTBnCCb signal and
asserts the TOBnb pin. When the count value matches D01, the counter generates the INTTBnCC0 signal,
deasserts the TOBnb pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the
one-shot pulse that is originally expected.
Remark n = 0, 1, a = 0 to 3, b = 1 to 3
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User’s Manual U18279EJ3V0UD