UPD70F3451GC-UBT-A Datasheet, PDF (1024/1191 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(2) Generation of exception in servicing program
Servicing program of maskable interrupt or exception
...
...
• EIPC saved to memory or register
• EIPSW saved to memory or register
...
• TRAP instruction
...
• Saved value restored to EIPSW
• Saved value restored to EIPC
• RETI instruction
← Exception such as TRAP instruction acknowledged.
The priority order for multiple interrupt servicing control has 8 levels, from 0 to 7 for each maskable interrupt
request signal (0 is the highest priority), but it can be set as desired via software. The priority order is set using
the xxPRn0 to xxPRn2 bits of the interrupt control request register (xxlCn), provided for each maskable
interrupt request signal. After system reset, an interrupt request signal is masked by the xxMKn bit and the
priority order is set to level 7 by the xxPRn0 to xxPRn2 bits.
The priority order of maskable interrupts is as follows.
(High) Level 0 > Level 1 > Level 2 > Level 3 > Level 4 > Level 5 > Level 6 > Level 7 (Low)
Interrupt servicing that has been suspended as a result of multiple servicing control is resumed after the
servicing of the higher priority interrupt has been completed and the RETI instruction has been executed.
A pending interrupt request signal is acknowledged after the current interrupt servicing has been completed
and the RETI instruction has been executed.
Caution In a non-maskable interrupt servicing routine (time until the RETI instruction is executed),
maskable interrupts are suspended and not acknowledged.
Remark xx: Identification name of each peripheral unit (see Table 20-2)
n: Peripheral unit number (see Table 20-2)
1022
User’s Manual U18279EJ3V0UD