HD404374 Datasheet, PDF (97/161 Pages) Renesas Technology Corp – Low-Voltage AS Microcomputers with On-Chip A/D Converter

HD404374/HD404384/HD404389/HD404082/HD404084 Series
Transfer end
(IFS←"1")
Disable interrupts
IFS←"0"
SMR1 write
State
Serial clock
wait state
SCK pin
(input)
1
SMR1
write
Yes
IFS=1?
No
Normal termination
Serial clock
error processing
(1) Serial clock error detection flowchart
Transfer state
Serial clock
wait state
Transfer state
(Noise)
Because the serial
interface returns to
the transfer state, a
2
3
4
5
6
7
8
write to SMR1
resets IFS.
IFS
Flag set by octal
counter reaching
000
(2) Serial clock error detection sequence
Flag reset by transfer
end processing
Figure 55 Example of Serial Clock Error Detection
Rev.5.00, Sep.11.2003, page 97 of 161