HD404374 Datasheet, PDF (37/161 Pages) Renesas Technology Corp – Low-Voltage AS Microcomputers with On-Chip A/D Converter

HD404374/HD404384/HD404389/HD404082/HD404084 Series
Table 3
Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt Control Bit _WU0
INT₀
Timer A
IE
1
1
1
IFWU•IMWU
1
0
0
IF0•IM0
*
1
0
IFTA•IMTA
*
*
1
IFTB•IMTB
*
*
*
IFTC•IMTC
*
*
*
IFAD•IMAD+IFS•IMS *
*
*
Note: * Operation is not affected whether the value is 0 or 1.
Timer B
1
0
0
0
1
*
*
Timer C
1
0
0
0
0
1
*
A/D or
Serial
1
0
0
0
0
0
1
Instruction cycle
1
2
3
4
5
6
Instruction
execution*
Interrupt
acceptance
Save to stack
IE reset
Save to stack
Vector address
generated
Execution of JMPL instruction
at vector address
Execution of
instruction at
start address of
interrupt routine
Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a 2cycle instruction.
Figure 9 Interrupt Sequence
Rev.5.00, Sep.11.2003, page 37 of 161