HD404374 Datasheet, PDF (62/161 Pages) Renesas Technology Corp – Low-Voltage AS Microcomputers with On-Chip A/D Converter

HD404374/HD404384/HD404389/HD404082/HD404084 Series
D Port
The D port consists of 10 I/O pins that are addressed bit-by-bit.
Ports D₀ to D₃ are source large-current I/O pins, and ports D₄ to D₇ are sink large-current I/O pins.
The D port can be set and reset by the SED and RED instructions or the SEDD and REDD instructions.
Output data is stored in the port data register (PDR) for each pin. The entire D port can be tested by the TD
or TDD instruction.
The D port output buffer is turned on and off by the D port data control registers (DCD0 to DCD2: $030 to
$032). The DCD registers are mapped onto memory addresses (figure 25).
Port D₀ is multiplexed as interrupt input pin INT₀. Setting as interrupt pin is performed by bit 0 (PMR00)
of port mode register 0 (PMR0: $008) (figure 26).
Data control registers (DCD0–2 : $030–$032)
(DCR0–2, 7 : $034–$036, $03B)
Register Name
DCDn
(n=0 to 2)
DCRm
(m=0 to 2, 7)
Bit
Read/Write
Reset
Bit name
Read/Write
Reset
Bit name
3
W
0
DCDn3
W
0
DCRm3
2
W
0
DCDn2
W
0
DCRm2
1
W
0
DCDn1
W
0
DCRm1
0
W
0
DCDn0
W
0
DCRm0
All bits
0
1
CMOS buffer control
CMOS buffer off (high impedance)
CMOS buffer active
Correspondence between each bit of DCD and DCR and ports
Register Name
DCD0
DCD1
DCD2
DCR0
DCR1
DCR2
DCR7
Bit 3
D3
D7
R13
R73
Bit 2
D2
D6
R22
R72
Bit 1
D1
D5
D9
R21
R71
Bit 0
D0
D4
D8
R00
R10
R20
R70
Figure 25 Data Control Registers (DCD, DCR)
Rev.5.00, Sep.11.2003, page 62 of 161