RX24T Datasheet, PDF (93/133 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24T Group
5.3.2
Reset Timing
5. Electrical Characteristics
Table 5.17 Reset Timing
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = AVCC1 = AVCC2 = VREF = VCC to 5.5 V, VSS = AVSS0 = AVSS1 = AVSS2 =
0 V, T_a = –40 to +85°C
Item
Symbol Min. Typ. Max.
Unit
Test Conditions
RES# pulse width
At power-on
Other than above
Wait time after RES# cancellation (at power-on)
Wait time after RES# cancellation
(during powered-on state)
t_RESWP
t_RESW
t_RESWT
t_RESWT
3
—
—
30
—
—
— 27.5 —
— 114 —
ms
Figure 5.29
μs
Figure 5.30
ms
Figure 5.29
μs
Figure 5.30
Independent watchdog timer reset period
t_RESWIW
—
1
— IWDT clock Figure 5.31
cycle
Software reset period
t_RESWSW
—
1
—
Wait time after independent watchdog timer reset cancellation*¹ t_RESW2
—
300
—
Wait time after software reset cancellation
t_RESW2
—
168
—
ICLK cycle
μs
μs
Note 1. When IWDTCR.CKS[3:0] = 0000b.
VCC
RES#
Internal reset
t_RESWP
Figure 5.29 Reset Input Timing at Power-On
t_RESWT
RES#
Internal reset
Figure 5.30 Reset Input Timing (1)
t_RESW
t_RESWT
Independent watchdog timer reset
Software reset
Internal reset
Figure 5.31 Reset Input Timing (2)
t_RESWIW, t_RESWSW
t_RESWT2
R01DS0257EJ0200 Rev.2.00
Apr 14, 2017
Page 93 of 133