RX24T Datasheet, PDF (119/133 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24T Group
5.9 Oscillation Stop Detection Timing
5. Electrical Characteristics
Table 5.38 Oscillation Stop Detection Timing
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 =AVCC1 = AVCC2 = VREF = VCC to 5.5 V, VSS = AVSS0 = AVSS1 = AVSS2 = 0 V,
Ta = –40 to +85°C
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Detection time
t_dr
—
—
1
ms Figure 5.60
Main clock
OSTDSR.OSTDF
Low-speed clock
ICLK
t_dr
When the main clock is selected
Figure 5.60 Oscillation Stop Detection Timing
Main clock
OSTDSR.OSTDF
PLL clock
ICLK
t_dr
When the PLL clock is selected
R01DS0257EJ0200 Rev.2.00
Apr 14, 2017
Page 119 of 133