RX24T Datasheet, PDF (100/133 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24T Group
5. Electrical Characteristics
Table 5.25 Timing of On-Chip Peripheral Modules (3)
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = AVCC1 = AVCC2 = VREF = VCC to 5.5 V, VSS = AVSS0 = AVSS1 = AVSS2 =
0 V, T_a = –40 to +85°C, C = 30pF
Item
Symbol
Min.
Max.
Unit*¹
Test
Conditions
Simple SCK clock cycle output (master)
SPI
SCK clock cycle input (slave)
SCK clock high pulse width
SCK clock low pulse width
SCK clock rise/fall time
Data input setup time (master)
VCC = 4.0 V or
above
t_SPcyc
t_SPCKWH
t_SPCKWL
t_SPCKr, t_SPCKf
t_SU
4
65536
t_Pcyc Figure 5.47
6
—
t_Pcyc
0.4
0.6
t_SPcyc
0.4
0.6
t_SPcyc
—
20
ns
40
—
ns
Figure 5.48,
Figure 5.49
VCC = 2.7 V or
above
65
—
Data input setup time (slave)
40
—
Data input hold time
SS input setup time
SS input hold time
Data output delay time (master)
Data output delay time (slave)
VCC = 4.0 V or
above
t_H
t_LEAD
t_LAG
t_OD
40
—
ns
3
—
t_SPcyc
3
—
t_SPcyc
—
40
ns
—
40
VCC = 2.7 V or
above
—
65
Data output hold time
Master
Slave
t_OH
–10
—
ns
–10
—
Data rise/fall time
SS input rise/fall time
Slave access time
Slave output release time
t_Dr, t_Df
—
20
ns
t_SSLr, t_SSLf
—
20
ns
t_SA
—
6
t_Pcyc Figure 5.50,
t_REL
—
6
t_Pcyc
Figure 5.51
Note 1. t_Pcyc: PCLK cycle
R01DS0257EJ0200 Rev.2.00
Apr 14, 2017
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