RX24T Datasheet, PDF (116/133 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24T Group
5. Electrical Characteristics
5.8 Power-On Reset Circuit and Voltage Detection Circuit Characteristics
Table 5.36 Power-On Reset Circuit and Voltage Detection Circuit Characteristics (1)
Conditions: VCC = 0 V to 5.5 V, AVCC0 = AVCC1 = AVCC2 = VREF = VCC to 5.5 V, VSS = AVSS0 = AVSS1 = AVSS2 = 0 V,
T_a = –40 to +85°C
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Voltage detection
level
Power-on reset (POR)
Voltage detection circuit
(LVD0)*¹
Voltage detection circuit
(LVD1)*²
Voltage detection circuit
(LVD2)*³
V_POR
V_{det0_0}
V_{det0_1}
V_{det0_2}
V_{det1_0}
V_{det1_1}
V_{det1_2}
V_{det1_3}
V_{det1_4}
V_{det1_5}
V_{det1_6}
V_{det1_7}
V_{det1_8}
V_{det2_0}
V_{det2_1}
V_{det2_2}
V_{det2_3}
1.35
3.67
2.70
2.37
4.12
3.98
3.86
3.68
2.99
2.89
2.79
2.68
2.57
4.08
3.95
3.82
3.62
1.50
3.84
2.82
2.51
4.29
4.14
4.02
3.84
3.10
3.00
2.90
2.79
2.68
4.29
4.14
4.02
3.84
1.65
3.97
3.00
2.67
4.42
4.28
4.16
3.98
3.29
3.19
3.09
2.98
2.87
4.48
4.35
4.22
4.02
V Figure 5.55, Figure 5.56
V
V Figure 5.58
At falling edge VCC
Figure 5.59
At falling edge VCC
Note:
Note 1.
Note 2.
Note 3.
These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage
detection level overlaps with that of the voltage detection circuit (LVD2), it cannot be specified which of LVD1 and LVD2 is used
for voltage detection.
n in the symbol V_{det0_n} denotes the value of the LVDS0[1:0] bits.
n in the symbol V_{det1_n} denotes the value of the LVDLVLR.LVD1LVL[3:0] bits.
n in the symbol V_{det2_n} denotes the value of the LVDLVLR.LVD2LVL[3:0] bits.
Table 5.37 Power-On Reset Circuit and Voltage Detection Circuit Characteristics (2)
Conditions: VCC = 0 V to 5.5 V, AVCC0 = AVCC1 = AVCC2 = VREF = VCC to 5.5 V, VSS = AVSS0 = AVSS1 = AVSS2 = 0 V,
Ta = –40 to +85°C
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Wait time after power-on
reset cancellation
At normal startup
t_POR
―
28.4
―
ms Figure 5.56
Wait time after voltage monitoring 0 reset
cancellation
t_LVD0
―
568
―
μs Figure 5.57
Wait time after voltage monitoring 1 reset
cancellation
Wait time after voltage monitoring 2 reset
cancellation
t_LVD1
t_LVD2
―
100
―
―
100
―
μs Figure 5.58
μs Figure 5.59
Response delay time
Minimum VCC down time*¹
t_det
―
―
350
μs Figure 5.55
t_VOFF
350
―
―
μs Figure 5.55, VCC = 1.0 V or
above
Power-on reset enable time
t_W(POR)
1
―
―
ms Figure 5.56, VCC = below 1.0
V
LVD operation stabilization time (after LVD is
enabled)
Hysteresis width (LVD0, LVD1 and LVD2)
Td_(E-A)
―
V_LVH
―
―
―
300
μs Figure 5.58, Figure 5.59
70
―
mV Vdet1_0 to 4 selected
60
―
Vdet0_0 to 2 selected
Vdet1_5 to 8 selected
LVD2 selected
R01DS0257EJ0200 Rev.2.00
Apr 14, 2017
Page 116 of 133