RX24T Datasheet, PDF (31/133 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24T Group
Single-chip mode^*1
0000 0000h
0000 8000h
0008 0000h
0010 0000h
0010 2000h
RAM^*2
Reserved area^*3
Peripheral I/O registers
On-chip ROM (E2 DataFlash)
(read only)
Reserved area^*3
007F C000h
007F C500h
007F FC00h
0080 0000h
Peripheral I/O registers
Reserved area^*3
Peripheral I/O registers
3. Address Space
Reserved area^*3
FFF8 0000h _{On-chip ROM (program ROM)}
FFFF FFFFh
(read only)^*2
Note 1. The address space in boot mode is the same as the address space in single-chip mode.
Note 2. The capacity of ROM/RAM differs depending on the products.
ROM (bytes)
RAM (bytes)
E2 DataFlash (bytes)
Capacity
512 K
Address
FFF8 0000h to FFFF FFFFh
Capacity
32 K
Address
0000 0000h to 0000 7FFFh
Capacity
8K
Address
0010 0000h to 0010 1FFFh
384 K
FFFA 0000h to FFFF FFFFh
256 K
FFFC 0000h to FFFF FFFFh
256 K
FFFC 0000h to FFFF FFFFh 16 K
0000 0000h to 0000 3FFFh
128 K
FFFE 0000h to FFFF FFFFh
Note: See Table 1.3 List of Products, for the product type name.
Note 3. Reserved areas should not be accessed.
Figure 3.1
Memory Map in Each Operating Mode
R01DS0257EJ0200 Rev.2.00
Apr 14, 2017
Page 31 of 133