RX24T Datasheet, PDF (2/133 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24T Group
1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different
packages.
Table 1.1 shows the outline of maximum specifications, and the numbers of peripheral modules and of channels of the
modules differ depending on chip version and the pin number on the package. For details, see Table 1.2, Comparison
of Functions for Different Packages.
Table 1.1
Outline of Specifications (1/4)
Classification Module/Function
Description
CPU
CPU
• Maximum operating frequency: 80 MHz
• 32-bit RX CPU (RX v2)
• Minimum instruction execution time: One instruction per clock cycle
• Address space: 4-Gbyte linear
• Register set
General purpose: Sixteen 32-bit registers
Control: Ten 32-bit registers
Accumulator: Two 72-bit registers
• Basic instructions: 75 Variable-length instruction format
• Floating-point instructions: 11
• DSP instructions: 23
• Addressing modes: 11
• Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
• On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit
• On-chip divider: 32-bit ÷ 32-bit → 32-bit
• Barrel shifter: 32 bits
• ROM cache: 2 Kbytes (disabled by default)
Memory
FPU
ROM
• Single precision (32-bit) floating point
• Data types and floating-point exceptions in conformance with the IEEE754 standard
• Capacity: 128 K/256 K/384 K/512 Kbytes
• Up to 32 MHz, no-wait memory access
32 to 80 MHz: wait states
• Off-board programming
• Programming/erasing method:
Serial programming (asynchronous serial communication), self-programming
RAM
E2 DataFlash
• Capacity: 16 K/32 Kbytes
• 80 MHz, no-wait memory access
• Capacity: 8 Kbytes
• Number of erase/write cycles: 1,000,000 (typ)
MCU operating mode
Single-chip mode
Clock
Clock generation circuit
• Main clock oscillator, low- and high-speed on-chip oscillators, PLL frequency synthesizer, and IWDT-
dedicated on-chip oscillator
• Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 80 MHz (at max.)
The MTU3 and GPT modules run in synchronization with the PCLKA: 80 MHz (at max.)
The peripheral modules other than MTU3 and GPT run in synchronization with the PCLKB: 40 MHz
(at max.)
ADCLK operated in S12AD runs in synchronization with the PCLKD: 40 MHz (at max.)
The flash memory peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)
Resets
RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and
software reset
Voltage detection Voltage detection circuit
(LVDAb)
• When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 0 is capable of selecting the detection voltage from 3 levels
Voltage detection circuit 1 is capable of selecting the detection voltage from 9 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels
Low power
consumption
Low power consumption
functions
• Module stop function
• Three low power consumption modes
Sleep mode, deep sleep mode, and software standby mode
Function for lower operating • Operating power control modes
power consumption
High-speed operating mode and middle-speed operating mode
R01DS0257EJ0200 Rev.2.00
Apr 14, 2017
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