RX24T Datasheet, PDF (117/133 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24T Group
5. Electrical Characteristics
Note:
Note 1.
These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage
detection level overlaps with that of the voltage detection circuit (LVD1), it cannot be specified which of LVD1 and LVD2 is used
for voltage detection.
The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V_POR, V_det0,
V_det1, and V_det2 for the POR/LVD.
VCC
V_POR
1.0 V
t_VOFF
Internal reset signal
(active-low)
Figure 5.55 Voltage Detection Reset Timing
t_det t_det t_POR
VCC
V_POR
1.0 V
Internal reset signal
(active-low)
t_w(POR)
*1
t_det t_POR
Note 1. t_w(POR) is the time required for a power-on reset to be enabled while the external power VCC is being held below the
valid voltage (1.0 V).
When VCC turns on, maintain t_w(POR) for 1.0 ms or more.
Figure 5.56 Power-On Reset Timing
VCC
V_det0
t_VOFF
V_LVH
Internal reset signal
(active-low)
t_det
Figure 5.57 Voltage Detection Circuit Timing (Vdet0)
R01DS0257EJ0200 Rev.2.00
Apr 14, 2017
t_det
t_LVD0
Page 117 of 133