RX24T Datasheet, PDF (27/133 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24T Group
2. CPU
Figure 2.1 shows register set of the CPU.
2. CPU
General-purpose register
b31
R0 (SP)^*1
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
DSP instruction register
b71
Control register
b0 b31
b0
ISP (Interrupt stack pointer)
USP (User stack pointer)
INTB (Interrupt table register)
PC (Program counter)
PSW (Processor status word)
BPC (Backup PC)
BPSW (Backup PSW)
FINTV (Fast interrupt vector register)
FPSW (Floating-point status word)
EXTB (Exception table register)
b0
ACC0 (Accumulator 0)
ACC1 (Accumulator 1)
Note 1. The stack pointer (SP) can be the interrupt stack pointer (ISP) or user stack pointer (USP), according to
the value of the U bit in the PSW.
Figure 2.1
Register Set of the CPU
R01DS0257EJ0200 Rev.2.00
Apr 14, 2017
Page 27 of 133