RX24T Datasheet, PDF (74/133 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24T Group
5. Electrical Characteristics
Chip
Chip
Item
Symbol
Version A
Typ.
*⁷
Max.
Version B
Typ.
*⁷
Max.
Unit
Test
Conditions
Supply
current
*¹
High-speed
operating
mode
Deep sleep
mode
No peripheral
operation*²
ICLK = 80 MHz
ICLK = 64 MHz
ICLK = 32 MHz
I_CC
3.4 — 3.4 — mA
2.9 — 2.9 —
2.5 — 2.5 —
ICLK = 16 MHz
2.3 — 2.3 —
ICLK = 8 MHz
2.2 — 2.2 —
All peripheral
operation:
Normal
ICLK = 80 MHz*³
ICLK = 64 MHz*⁴
ICLK = 32 MHz*⁵
17.7 — 22.2 —
14.4 — 17.9 —
10.9 — 12.9 —
ICLK = 16 MHz*⁵
6.6 — 7.6 —
ICLK = 8 MHz*⁵
4.3 — 4.8 —
Increase during BGO operation*⁶
2.5 — 2.5 —
Middle-speed Normal
No peripheral ICLK = 12 MHz*¹⁰ I_CC
operating
modes
operating
mode
operation*⁸
ICLK = 8 MHz
ICLK = 1 MHz
5.3 — 5.3 — mA
4.5 — 4.5 —
2.5 — 2.5 —
All peripheral
operation:
Normal*⁹
ICLK = 12 MHz*¹⁰
ICLK = 8 MHz
ICLK = 1 MHz
7.8 — 8.7 —
6.3 — 6.9 —
2.7 — 2.7 —
All peripheral
operation:
Max.*⁹
ICLK = 12 MHz*¹⁰
— 17.0 — 18.0
Sleep
mode
No peripheral ICLK = 12 MHz*¹⁰
operation*⁸ _{ICLK = 8 MHz}
2.6 — 2.6 —
2.7 — 2.7 —
ICLK = 1 MHz
2.2 — 2.2 —
All peripheral
operation:
Normal*⁹
ICLK = 12 MHz*¹⁰
ICLK = 8 MHz
ICLK = 1 MHz
6.0 — 6.7 —
5.1 — 5.6 —
2.5 — 2.5 —
Deep sleep No peripheral ICLK = 12 MHz*¹⁰
mode
operation*⁸ _{ICLK = 8 MHz}
1.8 — 1.8 —
2.1 — 2.1 —
ICLK = 1 MHz
2.1 — 2.1 —
All peripheral
operation:
Normal*⁹
ICLK = 12 MHz*¹⁰
ICLK = 8 MHz
ICLK = 1 MHz
5.0 — 5.7 —
4.3 — 4.8 —
2.3 — 2.3 —
Increase during BGO operation*⁶
2.5 — 2.5 —
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up
MOSs are in the off state.
Note 2. Supply of the clock signal to peripheral modules is stopped in this state. The clock source is PLL. FCLK, PCLKA, PCLKB, and
PCLKD are set to divided by 64.
Note 3. The clock signal to peripheral modules is supplied in this state. The clock source is PLL. FCLK is set to divided by 4. PCLKA is
set to divided by 1. PCLKB and PCLKD are set to divided by 2.
Note 4. The clock signal to peripheral modules is supplied in this state. The clock source is PLL. PCLKA is set to divided by 1. FCLK,
PCLKB, and PCLKD are set to divided by 2.
Note 5. The clock signal to peripheral modules is supplied in this state. The clock source is PLL. The frequencies of FCLK, PCLKA,
PCLKB, and PCLKD are same as ICLK.
Note 6. This is the increase when data is programmed to or erased from the ROM or E2 DataFlash during program execution.
Note 7. Values when VCC = 5 V.
Note 8. Supply of the clock signal to peripheral modules is stopped in this state. The clock source is PLL. FCLK, PCLKA, PCLKB, and
PCLKD are set to divided by 64.
Note 9. Supply of the clock signal to peripheral modules is stopped in this state. The clock source is PLL. The frequencies of FCLK,
PCLKA, PCLKB, and PCLKD are same as ICLK.
Note 10. When the frequency of PLL is 48 MHz.
R01DS0257EJ0200 Rev.2.00
Apr 14, 2017
Page 74 of 133