HD404328 Datasheet, PDF (91/96 Pages) Hitachi Semiconductor – 4 BIT SINGLE CHIP MICROCOMPUTER

HD404328 Series
During Transmit Clock Input
Item
Symbol Pin Min Typ Max Unit
Test Conditions
Notes
Transmit clock cycle time
t_Scyc
SCK 1.0 —
Transmit clock high width t_SCKH
SCK 0.3
—
Transmit clock low width
t_SCKL
SCK 0.3 —
Transmit clock rise time
t_SCKr
SCK —
—
—
t_cyc, t_subcyc
1, 2
—
t_Scyc
1
—
t_Scyc
1
100 ns
HD404324, HD404324U, 1
HD404326, HD404326U,
HD404328, HD404328U:
V_CC = 3.5 V to 6.0 V
HD4074329, HD4074329U: 1
V_CC = 3.5 V to 5.5 V
—
—
200 ns
1
Transmit clock fall time
t_SCKf
SCK —
—
100 ns
HD404324, HD404324U, 1
HD404326, HD404326U,
HD404328, HD404328U:
V_CC = 3.5 V to 6.0 V
HD4074329, HD4074329U: 1
V_CC = 3.5 V to 5.5 V
—
—
200 ns
1
Serial output data delay time t_DSO
SO —
—
300 ns
HD404324, HD404324U, 1
HD404326, HD404326U,
HD404328, HD404328U:
V_CC = 3.5 V to 6.0 V,
load shown in figure 53
HD4074329, HD4074329U: 1
V_CC = 3.5 V to 5.5 V,
load shown in figure 53
—
—
500 ns
Load shown in figure 53 1
Serial input data setup time t_SSI
SI
200 —
— ns
HD404324, HD404324U, 1
HD404326, HD404326U,
HD404328, HD404328U:
V_CC = 3.5 V to 6.0 V
HD4074329, HD4074329U: 1
V_CC = 3.5 V to 5.5 V
300 —
— ns
1
Serial input data hold time t_HSI
SI
150 —
— ns
HD404324, HD404324U, 1
HD404326, HD404326U,
HD404328, HD404328U:
V_CC = 3.5 V to 6.0 V
HD4074329, HD4074329U: 1
V_CC = 3.5 V to 5.5 V
300 —
— ns
1
Notes: 1. Refer to figure 52.
2. The t_subcyc unit applies when subactive mode is operating.
89