HD404328 Datasheet, PDF (65/96 Pages) Hitachi Semiconductor – 4 BIT SINGLE CHIP MICROCOMPUTER

HD404328 Series
Table 31 LCD Frame Periods for Different Duty Cycles
Static Duty Cycle
Instruction Cycle
Time
2 µs
LMR
Bit 3
0
Bit 2
0
CL0
512 Hz
Bit 3
0
Bit 2
1
CL1
1953 Hz
Bit 3
1
Bit 2
0
CL2
244 Hz
Bit 3
1
Bit 2
1
CL3*
122 Hz/64 Hz
1/2 Duty Cycle
Instruction Cycle
Time
2 µs
LMR
Bit 3
0
Bit 2
0
CL0
256 Hz
Bit 3
0
Bit 2
1
CL1
976.5 Hz
Bit 3
1
Bit 2
0
CL2
122 Hz
Bit 3
1
Bit 2
1
CL3*
61 Hz/32 Hz
1/3 Duty Cycle
Instruction Cycle
Time
2 µs
LMR
Bit 3
0
Bit 2
0
CL0
170.6 Hz
Bit 3
0
Bit 2
1
CL1
651 Hz
Bit 3
1
Bit 2
0
CL2
81.3 Hz
Bit 3
1
Bit 2
1
CL3*
40.6 Hz/21.3 Hz
1/4 Duty Cycle
LMR
Bit 3
Bit 2 Bit 3
Bit 2 Bit 3
Bit 2
Bit 3
Bit 2
0
0
0
1
1
0
1
1
Instruction Cycle
Time
CL0
CL1
CL2
CL3*
2 µs
128 Hz
488.2 Hz
61 Hz
30.5 Hz/16 Hz
Note:
* The division ratio depends on the value of bit 3 of timer mode register A (TMA); the first value is for
TMA3 = 0 and the second is for TMA3 = 1.
When TMA3 = 0, CL3 = f_cyc/4096
When TMA3 = 1, CL3 = 32.768 kHz/512.
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