HD404328 Datasheet, PDF (24/96 Pages) Hitachi Semiconductor – 4 BIT SINGLE CHIP MICROCOMPUTER

HD404328 Series
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as shown in table 4.
Table 4 Interrupt Enable Flag
IE
Interrupt Enabled/Disabled
0
Disabled
1
Enabled
External Interrupts (INT₀, INT₁): Specified by port mode register A (PMRA: $004).
External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): Set at the rising or falling
edges of the INT₀ and INT₁ inputs, as shown in table 5.
Table 5 External Interrupt Request Flags
IF0, IF1
0
1
Interrupt Request
No
Yes
IF0 is set at the falling edge of signals input to INT₀, and IF1 is set at the rising and falling edges of signals
input to INT₁. The INT₁ interrupt edge is selected by the interrupt mode register (IMR: $010), as shown in
figure 9.
Interrupt mode register (IMR): $010
3
2
1
0 Initial value: 0000, R/W: W
INT₁ detection edge selection
ZCD detection edge selection
IMR
Bit 3 Bit 2
0
0
1
0
1
1
ZCD Detection Edge
No detection
Falling-edge detection
Rising-edge detection
Double-edge detection
IMR
Bit 1 Bit 0
0
0
1
0
1
1
Figure 9 Interrupt Mode Register
INT₁ Detection Edge
No detection
Falling-edge detection
Rising-edge detection
Double-edge detection
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