HD404328 Datasheet, PDF (25/96 Pages) Hitachi Semiconductor – 4 BIT SINGLE CHIP MICROCOMPUTER

HD404328 Series
External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): Prevent (mask) interrupt requests
caused by the corresponding external interrupt request flags, as shown in table 6.
Table 6 External Interrupt Masks
IM0, IM1
0
1
Interrupt Request
Enabled
Disabled (Masked)
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as shown
in table 7.
Table 7 Timer A Interrupt Request Flag
IFTA
0
1
Interrupt Request
No
Yes
Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the
timer A interrupt request flag, as shown in table 8.
Table 8 Timer A Interrupt Mask
IMTA
0
1
Interrupt Request
Enabled
Disabled (Masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as shown in
table 9.
Table 9 Timer B Interrupt Request Flag
IFTB
0
1
Interrupt Request
No
Yes
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