HD404328 Datasheet, PDF (64/96 Pages) Hitachi Semiconductor – 4 BIT SINGLE CHIP MICROCOMPUTER

HD404328 Series
Table 29 LCD Control Register
LCR
LCR
LCR
Display in Watch Mode or
Bit 2 Subactive Mode
Bit 1 Power Switch On/Off Bit 0
Blank/Display
0
Off
0
Off
0
Blank
1
On
1
On
1
Display
Note: When using an LCD in watch mode or subactive mode, use the divided output of a 32-kHz oscillator
as the LCD clock and set bit 2 of the LCR to 1. If using the divided output of the system clock as the
LCD clock, always set bit 2 of the LCR to 0.
LCD Duty Cycle/Clock Control Register (LMR: $014): Four-bit write-only register which selects the
display duty cycle and LCD clock source, as shown in table 30. The dependence of frame frequency on
duty cycle is shown in table 31.
Table 30 LCD Duty Cycle/Clock Control Register
LMR
Bit 3 Bit 2 Bit 1 Bit 0
Duty Selection/Input Clock Selection
—
—
0
0
1/4 duty cycle
1
1/3 duty cycle
1
0
1/2 duty cycle
1
Static
0
0
—
—
CL0 (32.768/64 kHz when using a 32.768-kHz oscillator)
1
1
0
1
CL1 (f_cyc/256)
CL2 (f_cyc/2048)
CL3 (refer to table 31)
Note: f_cyc is the divided system clock output.
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