HD404328 Datasheet, PDF (26/96 Pages) Hitachi Semiconductor – 4 BIT SINGLE CHIP MICROCOMPUTER

HD404328 Series
Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the
timer B interrupt request flag, as shown in table 10.
Table 10 Timer B Interrupt Mask
IMTB
0
1
Interrupt Request
Enabled
Disabled (Masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as shown in
table 11.
Table 11 Timer C Interrupt Request Flag
IFTC
0
1
Interrupt Request
No
Yes
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the
timer C interrupt request flag, as shown in table 12.
Table 12 Timer C Interrupt Mask
IMTC
0
1
Interrupt Request
Enabled
Disabled (Masked)
Zero-Crossing Interrupt Request Flag (IFZC: $003, Bit 0): Set by a zero crossing of an AC input
signal, as shown in table 13. The interrupt edge is selected by the interrupt mode register (IMR: $010), as
shown in figure 9.
Table 13 Zero-Crossing Interrupt Request Flag
IFZC
0
1
Interrupt Request
No
Yes
Zero-Crossing Interrupt Mask (IMZC: $003, Bit 1): Prevents (masks) an interrupt request caused by
the zero-crossing interrupt request flag, as shown in table 14.
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