HD404328 Datasheet, PDF (56/96 Pages) Hitachi Semiconductor – 4 BIT SINGLE CHIP MICROCOMPUTER

HD404328 Series
If port mode register A (PMRA) is written to in transmit clock wait state or transfer state, the serial mode
register (SMR) must be written to, to initialize the serial interface. The serial interface then enters STS
wait state.
If the serial interface shifts from transfer state to another state, the octal counter returns to 000, setting the
serial interrupt request flag.
STS instruction wait state
(octal counter = 000,
transmit clock disabled)
SMR write
STS instruction
8 transmit clocks
(internal clock)
(IFS ← 1)
SMR write (IFS ← 1)
Transmit clock wait state
(octal counter = 000)
Transmit clock
8 transmit clocks (external clock)
STS instruction
(IFS ← 1)
Transfer state
(octal counter ≠ 000)
Figure 32 Serial Interface Mode Transitions
Transmit Clock Error Detection: The serial interface will malfunction if a spurious pulse caused by
external noise conflicts with a normal transmit clock during transmission. A transmit clock error of this
type can be detected as shown in figure 33.
If more than eight transmit clocks are input in transmit clock wait state, the serial interface’s state changes
to transfer, transmit clock wait, then back to transfer.
If the serial interface is set to STS wait state by writing data to the SMR after the serial interrupt request
flag has been reset, the flag is reset again.
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