HD404829R Datasheet, PDF (90/149 Pages) Renesas Technology Corp – AS Microcomputer Incorporating a LCD controller/Driver Circuit

HD404829R Series
Transfer completion
(IFS ← 1)
Interrupts inhibited
IFS ^← 0
SMRA write
Yes
IFS = 1?
Transmit clock
error processing
No
Normal
termination
Transmit clock error detection flowchart
State
Transmit clock
wait state
SCK pin (input)
1
SMRA write
Transfer state
Transmit clock wait state
Transfer state
Noise
2
3
4
5
6
7
8
Transfer state has been
entered by the transmit clock
error. When SMRA is written,
IFS is set.
IFS
Flag set because octal
counter reaches 000
Flag reset at
transfer completion
Transmit clock error detection procedure
Figure 73 Transmit Clock Error Detection
88