HD404829R Datasheet, PDF (78/149 Pages) Renesas Technology Corp – AS Microcomputer Incorporating a LCD controller/Driver Circuit

HD404829R Series
EVND
Edge detection
logic
Input capture
status flag
(ICSF)
Input capture
error flag
(ICEF)
Error control
logic
Read signal
Timer D interrupt
request flag
(IFTD)
System
clock
øPER
÷2
÷4
÷8
÷32
÷128
÷512
÷2048
Timer read register D
(TRDL)
(TRDU)
4
4
Timer counter D
(TCDL)
(TCDU)
Input capture
timer control
Overflow
3
Time mode
register D1
(TMD1)
2
Timer mode
register D2
(TMD2)
Edge
detection
control
Edge detection
selection register
2 (ESR2)
Data bus
Clock line
Signal line
Figure 62 Block Diagram of Timer D (Input Capture Timer)
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