HD404829R Datasheet, PDF (45/149 Pages) Renesas Technology Corp – AS Microcomputer Incorporating a LCD controller/Driver Circuit

HD404829R Series
System clock select register (SSR: $029)
Bit
3
2
1
0
Initial value
0
0
—
—
Read/Write
W
W
—
—
Bit name
SSR3 SSR2
—
—
SSR3
0
1
32-kHz oscillation stop
Oscillation operates in stop mode
Oscillation stops in stop mode
SSR1
0
1
System clock selection
f_OSC = 400 kHz to 1 MHz
f_OSC = 1.6 to 4.2 MHz
SSR2
0
1
32-kHz oscillation division
ratio selection
f_SUB = f_X/8
f_SUB = f_X/4
Note: SSR3 is cleared only by a RESET input. SSR3 will not be cleared
by a STOPC input duringstop mode, and will retain its value.
SSR3 will also not be cleared upon entering stop mode.
Figure 27 System Clock Select Register (SSR)
D₀
GND
X2
X1
RESET
OSC₂
OSC₁
TEST
AV_SS
GND
Figure 28 Typical Layouts of Crystal and Ceramic Oscillator
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