HD404829R Datasheet, PDF (26/149 Pages) Renesas Technology Corp – AS Microcomputer Incorporating a LCD controller/Driver Circuit

HD404829R Series
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt
Cuntrol Bit
IE
IF0 ^. IM0
IF1 ^. IM1
IFTA ^. IMTA
IFTB ^. IMTB
+ IF2 ^. IM2
IFTC ^. IMTC
+ IF3 ^. IM3
IFTD ^. IMTD
+ IF4 ^. IM4
IFAD ^. IMAD
+ IFS ^. IMS
INT₀
1
1
*
*
*
*
*
*
INT₁
1
0
1
*
*
*
*
*
Timer A
1
0
0
1
*
Timer B or
INT₂
1
0
0
0
1
Timer C or
INT₃
1
0
0
0
0
Timer D or
INT₄
1
0
0
0
0
*
*
1
0
*
*
*
1
*
*
*
*
Note: Bits marked * can be either 0 or 1. Their values have no effect on operation.
A/D or
Serial
1
0
0
0
0
0
0
1
Instruction cycles
1
2
3
4
5
6
Instruction
execution*
Interrupt
acceptance
Stacking
IE reset
Vector address
generation
Execution of JMPL
instruction at vector address
Note: * The stack is accessed and the IE reset after the instruction
is executed, even if it is a 2-cycle instruction.
Figure 10 Interrupt Processing Sequence
Execution of
instruction at
start address
of interrupt
routine
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