HD404829R Datasheet, PDF (28/149 Pages) Renesas Technology Corp – AS Microcomputer Incorporating a LCD controller/Driver Circuit

HD404829R Series
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.
Table 4 Interrupt Enable Flag (IE: $000, Bit 0)
Interrupt
IE
Enabled/Disabled
0
Disabled
1
Enabled
External Interrupts (INT₀, INT₁, INT₂–INT₄): Five external interrupt signals.
External Interrupt Request Flags (IF0–IF4: $000, $001, $022, $023): IF0 and IF1 are set at the falling
edge of signals input to INT₀ and INT₁, and IF2–IF4 are set at the rising or falling edge of signals input to
INT₂–INT₄, as listed in table 5. The INT₂–INT₄ interrupt edges are selected by the detection edge select
registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13.
Table 5 External Interrupt Request Flags (IF0–IF4: $000, $001, $022, $023)
IF0–IF4
0
1
Interrupt Request
No
Yes
Detection edge selection register 1 (ESR1: $026)
Bit
Initial value
Read/Write
Bit name
3
0
W
ESR13
2
0
W
ESR12
1
0
W
ESR11
0
0
W
ESR10
ESR13 ESR12 INT₃ detection edge
ESR11 ESR10 INT₂ detection edge
0
0
No detection
0
0
No detection
1
Falling-edge detection
1
Falling-edge detection
1
0
Rising-edge detection
1
0
Rising-edge detection
1
Double-edge detection^*
1
Double-edge detection
*
Note: * Both falling and rising edges are detected.
Figure 12 Detection Edge Selection Register 1 (ESR1)
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