HD404829R Datasheet, PDF (86/149 Pages) Renesas Technology Corp – AS Microcomputer Incorporating a LCD controller/Driver Circuit

HD404829R Series
Table 22 Serial Interface Operating Modes
SMRA
Bit 3
1
PMRA
Bit 1 Bit 0
0
0
1
1
0
1
Operating Mode
Continuous clock output mode
Transmit mode
Receive mode
Transmit/receive mode
Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to
000 by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit
clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000,
the serial interrupt request flag (IFS: $023, bit 2) is set, and the transfer stops.
When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t_cyc
to 8192t_cyc by setting bits 2 to 0 (SMRA2– SMRA0) of serial mode register A (SMRA: $005) and bit 0
(SMRB0) of serial mode register B (SMRB: $028) as listed in table 23.
Table 23 Serial Transmit Clock (Prescaler Output)
SMRB
Bit 0
0
Bit 2
0
1
1
0
1
SMRA
Bit 1
0
1
0
0
1
0
Bit 0
0
1
0
1
0
1
0
1
0
1
0
1
Prescaler Division Ratio
÷ 2048
÷ 512
÷ 128
÷ 32
÷8
÷2
÷ 4096
÷ 1024
÷ 256
÷ 64
÷ 16
÷4
Transmit Clock Frequency
4096t_cyc
1024t_cyc
256t_cyc
64t_cyc
16t_cyc
4t_cyc
8192t_cyc
2048t_cyc
512t_cyc
128t_cyc
32t_cyc
8t_cyc
Operating States: The serial interface has the following operating states; transitions between them are
shown in figure 71.
STS wait state
Transmit clock wait state
Transfer state
Continuous clock output state (only in internal clock mode)
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