HD404829R Datasheet, PDF (124/149 Pages) Renesas Technology Corp – AS Microcomputer Incorporating a LCD controller/Driver Circuit

HD404829R Series
Table 29 RAM Address Instructions
Operation
Mnemonic Operation Code
Function
Words/
Status Cycles
Load W from LWI i
0 0 1 1 1 1 0 0 i₁ i₀
i→W
1/1
immediate
Load X from LXI i
1 0 0 0 1 0 i₃ i₂ i₁ i₀
i→X
1/1
immediate
Load Y from LYI i
1 0 0 0 0 1 i₃ i₂ i₁ i₀
i→Y
1/1
immediate
Load W
LWA
010001 0000
A→W
2/2*
from A
000000 0000
Load X
LXA
001110 1000
A→X
1/1
from A
Load Y
LYA
001101 1000
A→Y
1/1
from A
Increment Y IY
000101 1100
Y+1→Y
NZ 1/1
Decrement Y DY
001101 1111
Y–1→Y
NB 1/1
Add A to Y
AYY
000101 0100
Y+A→Y
OVF 1/1
Subtract A
from Y
SYY
001101 0100
Y–A→Y
NB 1/1
Exchange X XSPX
000000 0001
X ↔ SPX
1/1
and SPX
Exchange Y XSPY
000000 0010
Y ↔ SPY
1/1
and SPY
Exchange X XSPXY
000000 0011
X ↔ SPX,
1/1
and SPX,
Y ↔ SPY
Y and SPY
Note: * Although the LAW and LWA instructions require an operand ($000) in the second word, the
assembler generates it automatically and thus there is no need to specify it explicitly.
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