HD404829R Datasheet, PDF (23/149 Pages) Renesas Technology Corp – AS Microcomputer Incorporating a LCD controller/Driver Circuit

HD404829R Series
Item
Carry flag
Accumulator
B register
W register
X/SPX register
Y/SPY register
Serial data register
RAM
RAM enable flag
Port mode
register C bit 2
System clock
select register bit 3
Abbr.
(CA)
(A)
(B)
(W)
(X/SPX)
(Y/SPY)
(SRL, SRU)
(RAME)
(PMRC2)
(SSR3)
Status After Cancel-
lation of Stop Mode by
STOPC Input
Status After Cancel-
lation of Stop Mode by
RESET Input
Pre-stop-mode values are not guaranteed;
values must be initialized by program
Pre-stop-mode values are retained
1
0
Pre-stop-mode
0
values are retained
Status After all Other Types
of Reset
Pre-MCU-reset values
are not guaranteed; val-
ues must be initialized by
program
0
0
Interrupts
The MCU has 11 interrupt sources: five external signals (INT₀, INT₁, INT₂–INT₄), four timer/ counters
(timers A, B, C, and D), serial interface, and A/D converter.
An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.
Some vector addresses are shared by two different interrupts. They are timer B and INT₂, timer C and
INT₃, timer D and INT₄, and A/D converter and serial interface interrupts. So the type of request that has
occurred must be checked at the beginning of interrupt processing.
Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are
reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions.
The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag
(IE) and the IF to 0 and the interrupt mask (IM) to 1.
A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector
addresses are listed in table 2, and interrupt processing conditions for the 11 interrupt sources are listed in
table 3.
An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.
The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in
figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
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