HD404829R Datasheet, PDF (30/149 Pages) Renesas Technology Corp – AS Microcomputer Incorporating a LCD controller/Driver Circuit

HD404829R Series
Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the
timer A interrupt request flag, as listed in table 8.
Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3)
IMTA–IMTD
0
1
Interrupt Request
Enabled
Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in
table 7.
Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the
timer B interrupt request flag, as listed in table 8.
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in
table 7.
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the
timer C interrupt request flag, as listed in table 8.
Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the
rising or falling of signals input to EVND when the input capture function is used, as listed in table 7.
Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the
timer D interrupt request flag, as listed in table 8.
Serial Interrupt Request Flag (IFS: $023, Bit 2): Set when data transfer is completed or when data
transfer is suspended, as listed in table 9.
Table 9 Serial Interrupt Request Flag (IFS: $023, Bit 2)
IFS
Interrupt Request
0
No
1
Yes
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