H8SX1622 Datasheet, PDF (899/1056 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 23 Clock Pulse Generator
23.3 PLL Circuit
The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a
factor of 4. The frequency multiplication factor is fixed. The phase difference is controlled so that
the timing of the rising edge of the internal clock is the same as that of the EXTAL pin signal.
23.4 Frequency Divider
23.4.1 1φ, Bφ, Pφ Frequency Dividers
The frequency divider divides the PLL clock to generate a 1/2, 1/4, or 1/8 clock. After bits ICK2
to ICK0, PCK 2 to PCK0, and BCK2 to BCK0 are modified, this LSI operates at the modified
frequency.
23.4.2 Aφ Frequency Divider
The frequency divider divides the frequency of the PLL clock to create 1/3, 1/4, 1/5, and 1/6
clocks. After the ACK2, ACK1, and ACK0 bits are rewritten, the ∆Σ A/D converter operates
according to the frequency available after change. Before rewriting these bits, you need to set the
∆Σ A/D converter's module stop bit to 1 so that the ∆Σ A/D converter is stopped. Setting this
frequency is recommended because of the characteristics of the ∆Σ A/D converter: that is, Aφ is
designed to produce maximum accuracy in the neighborhood of 25 MHz.
Rev. 1.00 Nov. 01, 2007 Page 871 of 1024
REJ09B0414-0100