H8SX1622 Datasheet, PDF (137/1056 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 6 Interrupt Controller
6.3.3
Interrupt Priority Registers A to I, K, L, P to R (IPRA to IPRI, IPRK, IPRL, IPRP
to IPRR)
IPR sets priory (levels 7 to 0) for interrupts other than NMI.
Setting a value in the range from B'000 to B'111 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4,
and 2 to 0 assigns a priority level to the corresponding interrupt. For the correspondence between
the interrupt sources and the IPR settings, see table 6.2.
Bit
15
14
13
12
11
10
9
8
Bit Name

IPR14
IPR13
IPR12

IPR10
IPR9
IPR8
Initial Value
0
1
1
1
0
1
1
1
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Bit Name

IPR6
IPR5
IPR4

IPR2
IPR1
IPR0
Initial Value
0
1
1
1
0
1
1
1
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Initial
Bit
Bit Name Value R/W Description
15

0
R
Reserved
This is a read-only bit and cannot be modified.
14
IPR14
1
13
IPR13
1
12
IPR12
1
R/W Sets the priority level of the corresponding interrupt
R/W ^source.
R/W ^{000: Priority level 0 (lowest)}
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (highest)
11

0
R
Reserved
This is a read-only bit and cannot be modified.
Rev. 1.00 Nov. 01, 2007 Page 109 of 1024
REJ09B0414-0100