H8SX1622 Datasheet, PDF (385/1056 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 10 Data Transfer Controller (DTC)
Table 10.3 Chain Transfer Conditions
1st Transfer
2nd Transfer
Transfer
Transfer
CHNE CHNS DISEL Counter*¹ CHNE CHNS DISEL Counter*¹ DTC Transfer
0

0
Not 0




Ends at 1st transfer
0

0
0*²




Ends at 1st transfer
0

1




Interrupt request to CPU
1
0


0

0
Not 0
Ends at 2nd transfer
0

0
0*²
Ends at 2nd transfer
0

1

Interrupt request to CPU
1
1
0
Not 0



Ends at 1st transfer
1
1

0*²
0

0
Not 0
Ends at 2nd transfer
0

0
0*²
Ends at 2nd transfer
0

1
Interrupt request to CPU
1
1
1
Not 0




Ends at 1st transfer
Interrupt request to CPU
Notes: 1. CRA in normal mode transfer, CRAL in repeat transfer mode, or CRB in block transfer
mode
2. When the contents of the CRAH is written to the CRAL in repeat transfer mode
10.5.1 Bus Cycle Division
When the transfer data size is word and the SAR and DAR values are not a multiple of 2, the bus
cycle is divided and the transfer data is read from or written to in bytes. Similarly, when the
transfer data size is longword and the SAR and DAR values are not a multiple of 4, the bus cycle
is divided and the transfer data is read from or written to in words.
Table 10.4 shows the relationship among, SAR, DAR, transfer data size, bus cycle divisions, and
access data size. Figure 10.5 shows the bus cycle division example.
Table 10.4 Number of Bus Cycle Divisions and Access Size
SAR and DAR Values Byte (B)
Address 4n
1 (B)
Address 2n + 1
1 (B)
Address 4n + 2
1 (B)
Specified Data Size
Word (W)
Longword (LW)
1 (W)
1 (LW)
2 (B-B)
3 (B-W-B)
1 (W)
2 (W-W)
Rev. 1.00 Nov. 01, 2007 Page 357 of 1024
REJ09B0414-0100