H8SX1622 Datasheet, PDF (309/1056 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 9 DMA Controller (DMAC)
Initial
Bit
Bit Name Value R/W Description
12
SARA4 0
R/W Source Address Extended Repeat Area
11
SARA3 0
10
SARA2 0
9
SARA1 0
8
SARA0 0
R/W Specify the extended repeat area on the source address
R/W
(DSAR). With the extended repeat area, the specified
lower address bits are updated and the remaining upper
R/W _{address bits are fixed. The extended repeat area size is}
R/W ^{specified from four bytes to 128 Mbytes in units of byte}
and a power of 2.
When the lower address is overflowed from the
extended repeat area by address update, the address
becomes the start address and the end address of the
area for address addition and subtraction, respectively.
When an overflow in the extended repeat area occurs
with the SARIE bit set to 1, an interrupt can be
requested. Table 9.3 shows the settings and areas of
the extended repeat area.
7
DARIE
0
R/W Destination Address Extended Repeat Area Overflow
Interrupt Enable
Enables/disables an interrupt request for an extended
area overflow on the destination address.
When an extended repeat area overflow on the
destination address occurs while this bit is set to 1, the
DTE bit in DMDR is cleared to 0. At this time, the ESIF
bit in DMDR is set to 1 to indicate an interrupt by an
extended repeat area overflow on the destination
address is requested.
When block transfer mode is used with the extended
repeat area function, an interrupt is requested after
completion of a 1-block size transfer. When setting the
DTE bit in DMDR of the channel for which the transfer
has been stopped to 1, the transfer is resumed from the
state when the transfer is stopped.
When the extended repeat area is not specified, this bit
is ignored.
0: Disables an interrupt request for an extended area
overflow on the destination address
1: Enables an interrupt request for an extended area
overflow on the destination address
6, 5 
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
Rev. 1.00 Nov. 01, 2007 Page 281 of 1024
REJ09B0414-0100