H8SX1622 Datasheet, PDF (285/1056 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 8 Bus Controller (BSC)
8.15 Bus Controller Operation in Reset
In a reset, this LSI, including the bus controller, enters the reset state immediately, and any
executing bus cycle is aborted.
8.16 Usage Notes
(1) Setting Registers
The BSC registers must be specified before accessing the external address space. In on-chip ROM
disabled mode, the BSC registers must be specified before accessing the external address space for
other than an instruction fetch access.
(2) External Bus Release Function and All-Module-Clock-Stop Mode
In this LSI, if the ACSE bit in MSTPCRA is set to 1, and then a SLEEP instruction is executed
with the setting for all peripheral module clocks to be stopped (MSTPCRA and MSTPCRB =
H'FFFFFFFF) or for operation of the 8-bit timer module alone (MSTPCRA = H'F[E to
0]FFFFFF), and a transition is made to the sleep state, the all-module-clock-stop mode is entered
in which the clock is also stopped for the bus controller and I/O ports. For details, see section 24,
Power-Down Modes.
In this state, the external bus release function is halted. To use the external bus release function in
sleep mode, the ACSE bit in MSTPCR must be cleared to 0. Conversely, if a SLEEP instruction to
place the chip in all-module-clock-stop mode is executed in the external bus released state, the
transition to all-module-clock-stop mode is deferred and performed until after the bus is
recovered.
(3) External Bus Release Function and Software Standby
In this LSI, internal bus master operation does not stop even while the bus is released, as long as
the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP
instruction to place the chip in software standby mode is executed while the external bus is
released, the transition to software standby mode is deferred and performed after the bus is
recovered.
Also, since clock oscillation halts in software standby mode, if the BREQ signal goes low in this
mode, indicating an external bus release request, the request cannot be answered until the chip has
recovered from the software standby mode.
Note that the BACK and BREQO pins are both in the high-impedance state in software standby
mode.
Rev. 1.00 Nov. 01, 2007 Page 257 of 1024
REJ09B0414-0100