H8SX1622 Datasheet, PDF (328/1056 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 9 DMA Controller (DMAC)
Figure 9.15 shows an example of the extended repeat area operation.
When the area represented by the lower three bits of DSAR (eight bytes)
is specified as the extended repeat area (SARA4 to SARA0 = B'00011)
External memory
Area specified
H'23FFFE
by DSAR
H'23FFFF
H'240000
H'240001
H'240000
H'240001
Repeat
H'240002
H'240002
H'240003
H'240003
H'240004
H'240004
H'240005
H'240005
H'240006
H'240006
H'240007
H'240008
H'240009
H'240007
An interrupt request by extended repeat area
overflow can be generated.
Figure 9.15 Example of Extended Repeat Area Operation
When an interrupt by an extended repeat area overflow is used in block transfer mode, the
following should be taken into consideration.
When a transfer is stopped by an interrupt by an extended repeat area overflow, the address
register must be set so that the block size is a power of 2 or the block size boundary is aligned with
the extended repeat area boundary. When an overflow on the extended repeat area occurs during a
transfer of one block, the interrupt by the overflow is suspended and the transfer overruns.
Rev. 1.00 Nov. 01, 2007 Page 300 of 1024
REJ09B0414-0100