H8SX1622 Datasheet, PDF (778/1056 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 19 ∆Σ A/D Converter
ADIE
ADST
ADF
Set*
Start A/D ^Set*
conversion
Clear*
Set*
Clear*
Channel 0 (ANDS0)
State of operation
Idle
Channel 1 (ANDS1)
State of operation
Idle
Channel 2 (ANDS2) _Idle
State of operation
Channel 3 (ANDS3) _Idle
State of operation
DSADDR0
DSADDR1
DSADDR2
A/D conversion 1
Idle
A/D conversion 2
Idle
Read the result
A/D conversion result 1
Read the result
A/D conversion result 2
DSADDR3
Note: * indicates execution of a software instruction.
Figure 19.3 Example of ∆Σ A/D Converter Operation (Single Mode for One Channel:
Channel 1)
Figure 19.4 shows an example of ∆Σ A/D converter operation (in multi-channel single mode with
channels 0 to 2 selected).
When A/D conversion is performed for two or more channels (multi-channel single mode), the
analog input on each of the selected channels is A/D converted once in sequence from channel 0,
as described below.
1. A/D conversion is started for the selected channels when the ADST bit in DSADCSR is set to
1 by software or by the input of a trigger signal selected by the TRGS1 and TRGS0 bits in
DSADCSR. Execution of A/D conversion is in order of rising channel number, so the order of
precedence starts from channel 0.
2. When A/D conversion is completed for channel n, the result is transferred to the corresponding
∆Σ A/D data register (DSADDRn, n = 0 to 5).
Rev. 1.00 Nov. 01, 2007 Page 750 of 1024
REJ09B0414-0100