H8SX1622 Datasheet, PDF (716/1056 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 17 I²C Bus Interface 2 (IIC2)
17.3.4 I²C Bus Interrupt Enable Register (ICIER)
ICIER enables or disables interrupt sources and the acknowledge bits, sets the acknowledge bits to
be transferred, and confirms the acknowledge bit to be received.
Bit
Bit Name
Initial Value
R/W
7
TIE
0
R/W
6
TEIE
0
R/W
5
RIE
0
R/W
4
NAKIE
0
R/W
3
STIE
0
R/W
2
ACKE
0
R/W
1
ACKBR
0
R
0
ACKBT
0
R/W
Initial
Bit
Bit Name Value R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit enables
or disables the transmit data empty interrupt (TXI)
request.
0: Transmit data empty interrupt (TXI) request is
disabled
1: Transmit data empty interrupt (TXI) request is
enabled
6
TEIE
0
R/W
Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt
(TEI) request at the rising of the ninth clock while the
TDRE bit in ICSR is set to 1. The TEI request can be
canceled by clearing the TEND bit or the TEIE bit to 0.
0: Transmit end interrupt (TEI) request is disabled
1: Transmit end interrupt (TEI) request is enabled
5
RIE
0
R/W
Receive Interrupt Enable
This bit enables or disables the receive full interrupt
(RXI) request when receive data is transferred from
ICDRS to ICDRR and the RDRF bit in ICSR is set to 1.
The RXI request can be canceled by clearing the
RDRF or RIE bit to 0.
0: Receive data full interrupt (RXI) request is disabled
1: Receive data full interrupt (RXI) request is enabled
Rev. 1.00 Nov. 01, 2007 Page 688 of 1024
REJ09B0414-0100