UPD70F3740GC-UEU-AX Datasheet, PDF (813/889 Pages) Renesas Technology Corp – RENESAS MCU

V850ES/JG3
CHAPTER 29 ELECTRICAL SPECIFICATIONS
RAM Retention Detection
(TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter
Detection voltage
Supply voltage rise time
Response time^Note
Minimum pulse width
Symbol
VRAMH
tRAMHTH
tRAMHD
tRAMHW
Conditions
VDD = 0 to 2.85 V
After VDD reaches 2.1 V
MIN.
TYP.
MAX.
Unit
1.9
2.0
2.1
V
0.002
ms
0.2
3.0
ms
0.2
ms
Note Time required to detect the detection voltage and set the RAMS.RAMF bit.
Supply voltage
(VDD)
Operating voltage (MIN.)
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
RAMS.RAMF bit
tRAMHTH
tRAMHD
Cleared by instruction
tRAMHW
tRAMHD
Time
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
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