UPD70F3740GC-UEU-AX Datasheet, PDF (298/889 Pages) Renesas Technology Corp – RENESAS MCU

V850ES/JG3
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
(2) TMQ0 control register 1 (TQ0CTL1)
The TQ0CTL1 register is an 8-bit register that controls the operation of TMQ0.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
7
TQ0CTL1
0
R/W Address: FFFFF541H
<6>
<5>
4
3
TQ0EST TQ0EEE 0
0
2
1
0
TQ0MD2 TQ0MD1 TQ0MD0
TQ0EST
Software trigger control
0
−
1 ^{Generate a valid signal for external trigger input.}
• In one-shot pulse output mode: A one-shot pulse is output with writing
1 to the TQ0EST bit as the trigger.
• In external trigger pulse output mode: A PWM waveform is output with
writing 1 to the TQ0EST bit as
the trigger.
TQ0EEE
Count clock selection
0 Disable operation with external event count input.
(Perform counting with the count clock selected by the TQ0CTL0.TQ0CK0
to TQ0CK2 bits.)
1
Enable operation with external event count input.
(Perform counting at the valid edge of the external event count input
signal.)
The TQ0EEE bit selects whether counting is performed with the internal count clock
or the valid edge of the external event count input.
TQ0MD2 TQ0MD1 TQ0MD0
Timer mode selection
0
0
0
Interval timer mode
0
0
1
External event count mode
0
1
0
External trigger pulse output mode
0
1
1
One-shot pulse output mode
1
0
0
PWM output mode
1
0
1
Free-running timer mode
1
1
0
Pulse width measurement mode
1
1
1
Setting prohibited
Cautions 1. The TQ0EST bit is valid only in the external trigger pulse output
mode or one-shot pulse output mode. In any other mode, writing 1
to this bit is ignored.
2. External event count input is selected in the external event count
mode regardless of the value of the TQ0EEE bit.
3. Set the TQ0EEE and TQ0MD2 to TQ0MD0 bits when the
TQ0CTL0.TQ0CE bit = 0. (The same value can be written when the
TQ0CE bit = 1.) The operation is not guaranteed when rewriting is
performed with the TQ0CE bit = 1. If rewriting was mistakenly
performed, clear the TQ0CE bit to 0 and then set the bits again.
4. Be sure to clear bits 3, 4, and 7 to “0”.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Page 282 of 870