UPD70F3740GC-UEU-AX Datasheet, PDF (170/889 Pages) Renesas Technology Corp – RENESAS MCU

V850ES/JG3
CHAPTER 5 BUS CONTROL FUNCTION
5.5.3 Access by bus size
The V850ES/JG3 accesses the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size
is as follows.
• The bus size of the on-chip peripheral I/O is fixed to 16 bits.
• The bus size of the external memory is selectable from 8 bits or 16 bits (by using the BSC register).
The operation when each of the above is accessed is described below. All data is accessed starting from the lower side.
The V850ES/JG3 supports only the little-endian format.
Figure 5-2. Little-Endian Address in Word
31
24 23
16 15
87
0
000BH
000AH
0009H
0008H
0007H
0006H
0005H
0004H
0003H
0002H
0001H
0000H
(1) Data space
The V850ES/JG3 has an address misalign function.
With this function, data can be placed at all addresses, regardless of the format of the data (word data or halfword
data). However, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least
twice, causing the bus efficiency to drop.
(a) Halfword-length data access
A byte-length bus cycle is generated twice if the least significant bit of the address is 1.
(b) Word-length data access
(i) A byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if
the least significant bit of the address is 1.
(ii) A halfword-length bus cycle is generated twice if the lower 2 bits of the address are 10.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Page 154 of 870