UPD70F3740GC-UEU-AX Datasheet, PDF (187/889 Pages) Renesas Technology Corp – RENESAS MCU

V850ES/JG3
CHAPTER 5 BUS CONTROL FUNCTION
Figure 5-8. Multiplexed Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access)
CLKOUT
HLDRQ
HLDAK
A21 to A16
AD15 to AD0
ASTB
RD
T1
T2
T3
TI^Note TH
TH
TH
TH
TI^Note
T1
T2
T3
A1
A1
D1
Undefined
Undefined
Undefined
A2
Undefined A2 D2
Note This idle state (TI) does not depend on the BCC register settings.
Remarks 1. See Table 2-2 for the pin statuses in the bus hold mode.
2. The broken lines indicate high impedance.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Page 171 of 870