UPD70F3740GC-UEU-AX Datasheet, PDF (193/889 Pages) Renesas Technology Corp – RENESAS MCU

V850ES/JG3
CHAPTER 6 CLOCK GENERATION FUNCTION
(1) Main clock oscillator
The main resonator oscillates the following frequencies (fX).
• In clock-through mode
fX = 2.5 to 10 MHz
• In PLL mode
fX = 2.5 to 5 MHz (×4)
fX = 2.5 to 4 MHz (×8)
(2) Subclock oscillator
The sub-resonator oscillates a frequency of 32.768 kHz (fXT).
(3) Main clock oscillator stop control
This circuit generates a control signal that stops oscillation of the main clock oscillator.
Oscillation of the main clock oscillator is stopped in the STOP mode or when the PCC.MCK bit = 1 (valid only when
the PCC.CLS bit = 1).
(4) Internal oscillator
Oscillates a frequency (fR) of 220 kHz (TYP.).
(5) Prescaler 1
This prescaler generates the clock (fXX to fXX/1,024) to be supplied to the following on-chip peripheral functions:
TMP0 to TMP5, TMQ0, TMM0, CSIB0 to CSIB4, UARTA0 to UARTA2, I²C00 to I²C02, ADC, and WDT2
(6) Prescaler 2
This circuit divides the main clock (fXX).
The clock generated by prescaler 2 (fXX to fXX/32) is supplied to the selector that generates the CPU clock (fCPU)
and internal system clock (fCLK).
fCLK is the clock supplied to the INTC, ROM, and RAM blocks, and can be output from the CLKOUT pin.
(7) Prescaler 3
This circuit divides the clock generated by the main clock oscillator (fX) to a specific frequency (32.768 kHz) and
supplies that clock to the watch timer block.
For details, see CHAPTER 10 WATCH TIMER FUNCTIONS.
(8) PLL
This circuit multiplies the clock generated by the main clock oscillator (fX) by 4 or 8.
It operates in two modes: clock-through mode in which fX is output as is, and PLL mode in which a multiplied clock
is output. These modes can be selected by using the PLLCTL.SELPLL bit.
Whether the clock is multiplied by 4 or 8 is selected by the CKC.CKDIV0 bit, and PLL is started or stopped by the
PLLCTL.PLLON bit.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Page 177 of 870