UPD70F3740GC-UEU-AX Datasheet, PDF (286/889 Pages) Renesas Technology Corp – RENESAS MCU

V850ES/JG3
CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
Figure 7-36. Register Setting in Pulse Width Measurement Mode (2/2)
(d) TMPn option register 0 (TPnOPT0)
TPnCCS1 TPnCCS0
TPnOVF
TPnOPT0
0
0
0
0
0
0
0
0/1
Overflow flag
(e) TMPn counter read buffer register (TPnCNT)
The value of the 16-bit counter can be read by reading the TPnCNT register.
(f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1)
These registers store the count value of the 16-bit counter when the valid edge input to the TIPnm pin is
detected.
Remarks 1. TMPn I/O control register 0 (TPnIOC0) and TMPn I/O control register 2 (TPnIOC2) are not
used in the pulse width measurement mode.
2. n = 0 to 5
m = 0, 1
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Page 270 of 870