UPD70F3740GC-UEU-AX Datasheet, PDF (543/889 Pages) Renesas Technology Corp – RENESAS MCU

V850ES/JG3
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
16.6.14 Clock timing
(i) Communication type 1 (CBnCKP and CBnDAP bits = 00)
SCKBn pin
SIBn capture
SOBn pin
Reg-R/W
INTCBnT
interrupt^{Note 1}
INTCBnR
interrupt^{Note 2}
CBnTSF bit
D7
D6
D5
D4
D3
D2
D1
D0
(1/2)
(ii) Communication type 3 (CBnCKP and CBnDAP bits = 10)
SCKBn pin
SIBn capture
SOBn pin
D7
D6
D5
D4
D3
D2
D1
D0
Reg-R/W
INTCBnT
interrupt^{Note 1}
INTCBnR
interrupt^{Note 2}
CBnTSF bit
Notes 1. The INTCBnT interrupt is set when the data written to the CBnTX register is transferred to the data shift
register in the continuous transmission or continuous transmission/reception mode. In the single
transmission or single transmission/reception mode, the INTCBnT interrupt request signal is not
generated, but the INTCBnR interrupt request signal is generated upon end of communication.
2. The INTCBnR interrupt occurs if reception is correctly ended and receive data is ready in the CBnRX
register while reception is enabled. In the single mode, the INTCBnR interrupt request signal is
generated even in the transmission mode, upon end of communication.
Caution In single transfer mode, writing to the CBnTX register with the CBnTSF bit set to 1 is ignored.
This has no influence on the operation during transfer.
For example, if the next data is written to the CBnTX register when DMA is started by generating
the INTCBnR signal, the written data is not transferred because the CBnTSF bit is set to 1.
Use the continuous transfer mode, not the single transfer mode, for such applications.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Page 527 of 870