7721 Datasheet, PDF (71/577 Pages) List of Unclassifed Manufacturers – H Bridge Power Module

RESET
4.1 Hardware reset
Address
Register name
6016
6116
6216
6316
6416
6516
6616
6716
6816
6916
6A16
6B16
6C16
6D16
6E16
6F16
7016
7116
7216
7316
7416
7516
7616
7716
7816
7916
7A16
7B16
7C16
7D16
7E16
7F16
Watchdog timer register
Watchdog timer frequency select register
Real-time output control register
DRAM control register
Refresh timer
DM AC control register L
DM AC control register H
DM A0 interrupt control register
DM A1 interrupt control register
DM A2 interrupt control register
DM A3 interrupt control register
A-D conversion interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
Access characteristics
b7
b0
(Note 5)
RW
RW
RW
RW
WO
(Note 7)
RW
RW
WO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
State immediately after reset
b7
b0
?(Note 6)
?
0
000 0 000 0
RW
?
000 00 00 0
?
?
?
000 0??0 0
000 00 00 0
?
?
?
000 0
?
0 000
?
0 000
?
0 000
?
000 0
?
0 000
?
0 000
?
0 000
?
0 000
?
0 000
?
0 000
?
0 000
?
0 000
?
0 000
?
0 000
?
0 000
?
0 000
? 0 00 000
? 0 00 000
? 0 00 000
Notes 5: By writing dummy data to address 6016, the value “FFF16” is set to the watchdog timer.
The dummy data is not retained anywhere.
6: The value “FFF16” is set to the watchdog timer. (Refer to “CHAPTER 15. WATCHDOG TIMER.”)
7: It is possible to read the bit state at reading. When writing “0” to this bit, this bit becomes “0.”
But when writing “1” to this bit, this bit does not change.
Fig. 4.1.7 State of SFR and internal RAM areas immediately after reset (4)
4–8
7721 Group User’s Manual