7721 Datasheet, PDF (210/577 Pages) List of Unclassifed Manufacturers – H Bridge Power Module

SERIAL I/O
11.2 Block description
11.2.3 UARTi transmit/receive control register 1
Figure 11.2.4 shows the structure of UARTi transmit/receive control register 1. For bits 4 to 7, refer to
section “11.3.6 Processing on detecting overrun error” and “11.4.7 Processing on detecting error.”
b7 b6 b5 b4 b3 b2 b1 b0
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
Bit
Bit name
0 Transmit enable bit
1 Transmit buffer empty flag
Functions
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in transmit buffer
register
1 : No data present in transmit
buffer register
At reset RW
0
RW
1
RO
2 Receive enable bit
3 Receive complete flag
0 : Reception disabled
1 : Reception enabled
0 : No data present in receive
buffer register
1 : Data present in receive buffer
register
0
RW
0
RO
4 Overrun error flag
(Note 1) ^{0 : No overrun error}
1 : Overrun error detected
0
RO
5 Framing error flag ^{(Notes 1, 2)} 0 : No framing error
(Valid in UART mode)
1 : Framing error detected
6 Parity error flag ^{(Notes 1, 2)} _{0 : No parity error}
(Valid in UART mode)
1 : Parity error detected
0
RO
0
RO
7 Error sum flag
(Notes 1, 2) 0 : No error
(Valid in UART mode)
1 : Error detected
0
RO
Notes 1: Bit 4 is cleared to “0” when the receive enable bit is cleared to “0” or when the serial
I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) are cleared to “0002.”
Bits 5 and 6 are cleared to “0” when one of the following is performed:
•Clearing the receive enable bit to “0”
•Reading the low-order byte of the UARTi receive buffer register (addresses 3616, 3E16)
out
•Clearing the serial I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) to “0002”
Bit 7 is cleared to “0” when all of bits 4 to 6 become “0.”
2: Bits 5 to 7 are invalid in the clock synchronous serial I/O mode.
Fig. 11.2.4 Structure of UARTi transmit/receive control register 1
7721 Group User’s Manual
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