7721 Datasheet, PDF (291/577 Pages) List of Unclassifed Manufacturers – H Bridge Power Module

DMA CONTROLLER
13.2 Block description
13.2.4 Source address register i (SARi)
Source address register i (hereafter called SARi) is a 24-bit register with a latch.
SARi indicates the transfer source address of the data to be transferred next.
The SARi latch has the following functions:
• Maintains the value written to the address of SARi (in the single transfer and repeat transfer modes).
• Indicates the start address of the transfer parameter memory of the next block (in the array chain
transfer and link array chain transfer modes).
When a value is written into the address of SARi, the same value is written into SARi and the SARi latch.
When writing a value to the address of SARi, all 24 bits must be written.
The contents of SARi can be read by reading the address of SARi; however, the value of the SARi latch
cannot be read. (Refer to “Tables 13.2.4 and 13.2.5.”)
13.2.5 Destination address register i (DARi)
Destination address register i (hereafter called DARi) is a 24-bit register with a latch.
DARi indicates the transfer destination address of the data to be transferred next.
The DARi latch maintains the value written to the address of DARi.
When a value is written into the address of DARi, the same value is written into DARi and the DARi latch.
When writing a value to the address of DARi, all 24 bits must be written.
The contents of DARi can be read by reading the address of DARi; however, the value of the DARi latch
cannot be read. (Refer to “Tables 13.2.4 and 13.2.5.”)
13.2.6 Transfer counter register i (TCRi)
Transfer counter register i (hereafter called TCRi) is a 24-bit register with a latch.
TCRi indicates the number of remaining bytes of the block under transfer.
The TCRi latch has the following functions:
• Maintains the value written to the address of TCRi (in the single transfer and repeat transfer modes).
• Indicates the number of remaining blocks (in the array chain transfer mode).
When a value is written into the address of TCRi, the same value is written into TCRi and the TCRi latch.
When writing a value to the address of TCRi, all 24 bits must be written.
The contents of TCRi can be read by reading the address of TCRi; however, the value of the TCRi latch
cannot be read. (Refer to “Tables 13.2.4 and 13.2.5.”)
Table 13.2.4 Addresses of SARi, DARi, and TCRi
Channel
Source address register i
(SARi)
Destination address
register i (DARi)
0
1FC216–1FC016
1FC616–1FC416
1
1FD216–1FD016
1FD616–1FD416
2
1FE216–1FE016
1FE616–1FE416
3
1FF216–1FF016
1FF616–1FF416
Transfer counter register i
(TCRi)
1FCA16–1FC816
1FDA16–1FD816
1FEA16–1FE8₁₆
1FFA16–1FF816
13-12
7721 Group User’s Manual