7721 Datasheet, PDF (329/577 Pages) List of Unclassifed Manufacturers – H Bridge Power Module

DMA CONTROLLER
13.4 Operation
[Precautions for burst transfer mode]
1. In the burst transfer mode (edge sense), the DMAi request bit is cleared to “0” when the transfer of an
entire batch of data is complete or the transfer is forced into termination. Therefore, another DMA request
of the same channel i is invalid if generated during DMAi transfer.
1-unit transfer
Transition of right to use bus
Termination processing _{(from DMAC to CPU)}
E
DMAi request bit is set to “0.”
Fig. 13.4.10 Timing when clearing DMAi request bit to “0” in burst transfer mode
2. Because interrupt priority levels are determined while the CPU fetches an operation code, interrupt
requests are not accepted during a DMA transfer. In the burst transfer mode (edge sense), therefore,
interrupt requests cannot be accepted until the transfer of an entire batch of data is complete or the
transfer is forced into termination.
13-50
7721 Group User’s Manual