7721 Datasheet, PDF (401/577 Pages) List of Unclassifed Manufacturers – H Bridge Power Module

WATCHDOG TIMER
15.2 Operation description
15.2.2 Stop period
Watchdog timer stops operation in the following period:
Œ Hold state (Refer to section “3.4 Hold function.”)
 During DMAC operation (Refer to “CHAPTER 13. DMA CONTROLLER.”)
Ž During DRAM refresh (Refer to “CHAPTER 14. DRAM CONTROLLER.”)
 Stop mode
When states Œ to Ž are terminated, Watchdog timer restarts counting from the state before it stops
operation. For Watchdog timer’s operation when state  is terminated, refer to section “15.2.3 Operation
in Stop mode.”
15.2.3 Operation in Stop mode
In Stop mode, Watchdog timer stops operation. Immediately after Stop mode is terminated, Watchdog timer
operates as follows. (Refer to section “5.3 Stop mode.”)
(1) When Stop mode is terminated by hardware reset
Supply of φ and φCPU starts immediately after Stop mode is terminated, and the microcomputer
performs “operation after reset.” (Refer to “CHAPTER 4. RESET.”) The watchdog timer frequency
select bit becomes “0,” and Watchdog timer starts counting of f512 from “FFF16.”
(2) When Stop mode is terminated by interrupt request occurrence
Immediately after Stop mode is terminated, Watchdog timer starts counting of f32 from “FFF16” regardless
of the contents of watchdog timer frequency select bit (bit 0 at address 6116). Supply of φ and φCPU
starts when Watchdog timer’s most significant bit becomes “0.” (At this time, a watchdog timer
interrupt request does not occur.)
When supply of φCPU starts, the microcomputer executes the routine of the interrupt which is used to
terminate Stop mode. Watchdog timer restarts counting of the count source (f32 or f512), which was
counted immediately before executing the STP instruction, from “FFF16.”
15–6
7721 Group User’s Manual